Compute Express Link - Wikipedia

CXL is built on the PCI Express (PCIe) physical and electrical interface with protocols in three areas: input/output (I/O), memory, and cache coherence. ComputeExpressLink FromWikipedia,thefreeencyclopedia Jumptonavigation Jumptosearch Openstandardprocessorinterconnectionfordatacenters ComputeExpressLinkYearcreated2019;2 yearsago (2019)SpeedFullduplex1.x,2.x(32GT/s):3.938GB/s(×1)63.01GB/s(×16)Websitewww.computeexpresslink.org ComputeExpressLink(CXL)isanopenstandardforhigh-speedcentralprocessingunit(CPU)-to-deviceandCPU-to-memoryconnections,designedforhighperformancedatacentercomputers.[1][2][3][4]CXLisbuiltonthePCIExpress(PCIe)physicalandelectricalinterfacewithprotocolsinthreeareas:input/output(I/O),memory,andcachecoherence. Contents 1History 1.1CXLSpecification1.0 1.2CXLSpecification1.1 1.3CXLSpecification2.0 2Seealso 3References 4Externallinks History[edit] FoundingmemberswereAlibabaGroup, CiscoSystems, DellEMC, Facebook, Google, HewlettPackardEnterprise(HPE), Huawei, IntelCorporationandMicrosoft.[5] Sincethen,manyotherswerelistedontheirwebsite. OnApril2,2019,IntelannouncedtheirfamilyofAgilexFPGAsfeaturingCXL.[6] OnMay11,2021,SamsungannouncedaDDR5basedmemoryexpansionmodulethatallowsforterabytelevelmemoryexpansionalongwithhighperformanceforuseindatacentresandpotentiallynextgenerationPCs.[7] OnApril2,2020,theComputeExpressLinkandGen-ZConsortiumsannouncedtheirexecutionofamemorandumofunderstanding(MoU),describingamutualplanforcollaborationbetweenthetwoorganizations.[8][9]InNovember2021theCXLConsortiumandtheGenZConsortiumsignedaletterofintentforGen-ZtotransferitsspecificationsandassetstoCXL,leavingCXLasthesoleindustrystandardmovingforward.[10] Specificationsreleasedincludethefollowing. CXLSpecification1.0[edit] OnMarch11,2019,theCXLSpecification1.0basedonPCIe5.0wasreleased.ThefoundingpromotermembersoftheCXLspecificationincluded:AlibabaGroup,CiscoSystems,DellEMC,Facebook,Google,HewlettPackardEnterprise(HPE),Huawei,Intel,andMicrosoft.[11] CXLSpecification1.1[edit] InJune,2019,theCXLSpecification1.1wasreleased. OnJuly18,2019,AdvancedMicroDevices(AMD)joinedCXL.[12] CXLSpecification2.0[edit] OnNovember10,2020,theCXLSpecification2.0wasreleased.ThereisnobandwidthincreasefromCXL1.x,becauseCXL2.0stillutilizesPCIe5.0. Seealso[edit] Cachecoherentinterconnectforaccelerators(CCIX) CoherentAcceleratorProcessorInterface(CAPI) Gen-Z Omni-Path References[edit] ^"ABOUTCXL".ComputeExpressLink.Retrieved2019-08-09. ^"SynopsysDeliversIndustry'sFirstComputeExpressLink(CXL)IPSolutionforBreakthroughPerformanceinData-IntensiveSoCs".finance.yahoo.com.Yahoo!Finance.Retrieved2019-11-09. ^"AMilestoneinMovingData".IntelNewsroom.Intel.Retrieved2019-11-09. ^"ComputeExpressLinkConsortium(CXL)OfficiallyIncorporates;AnnouncesExpandedBoardofDirectors".www.businesswire.com.BusinessWire.2019-09-17.Retrieved2019-11-09. ^"ComputeExpressLink:OurMembers".CXLConsortium.2020.Retrieved2020-09-25. ^"HowdothenewIntelAgilexFPGAfamilyandtheCXLcoherentinterconnectfabricintersect?"[email protected]. ^"SamsungUnveilsIndustry-FirstMemoryModuleIncorporatingNewCXLInterconnectStandard".Samsung.2021-05-11.Retrieved2021-05-11. ^"CXLConsortiumandGen-ZConsortiumAnnounceMOUAgreement"(PDF).Beaverton,Oregon.April2,2020.RetrievedSeptember25,2020. ^"CXLConsortiumandGen-ZConsortiumAnnounceMOUAgreement".April2,2020.RetrievedApril11,2020. ^CXLConsortiumstatement,10November2021 ^Cutress,Ian."CXLSpecification1.0Released:NewIndustryHigh-SpeedInterconnectFromIntel".Anandtech.Retrieved2019-08-09. ^Papermaster,Mark(July18,2019)."AMDJoinsConsortiatoAdvanceCXL,aNewHigh-SpeedInterconnectforBreakthroughPerformance".Community.AMD.Retrieved2020-09-25. Externallinks[edit] Officialwebsite vteTechnicalanddefactostandardsforwiredcomputerbusesGeneral Systembus Front-sidebus Back-sidebus Daisychain Controlbus Addressbus Buscontention Busmastering Networkonachip Plugandplay Listofbusbandwidths Standards SS-50bus S-100bus Multibus Unibus VAXBI MBus STDBus SMBus Q-Bus EuropeCardBus ISA STEbus ZorroII ZorroIII CAMAC FASTBUS LPC HPPrecisionBus EISA VME VXI VXS NuBus TURBOchannel MCA SBus VLB PCI PXI HPGSCbus InfiniBand Ethernet UPA PCIExtended(PCI-X) AGP PCIExpress(PCIe) ComputeExpressLink(CXL) CoherentAcceleratorProcessorInterface(CAPI) DirectMediaInterface(DMI) RapidIO IntelQuickPathInterconnect NVLink HyperTransport InfinityFabric IntelUltraPathInterconnect Storage ST-506 ESDI IPI SMD ParallelATA(PATA) SSA DSSI HIPPI SerialATA(SATA) SCSI Parallel SAS FibreChannel SATAe PCIExpress(viaAHCIorNVMelogicaldeviceinterface) Peripheral AppleDesktopBus AtariSIO DCB Commodorebus HP-IL HIL MIDI RS-232 RS-422 RS-423 RS-485 Lightning DMX512-A IEEE-488(GPIB) IEEE-1284(parallelport) UNI/O 1-Wire I²C(ACCESS.bus,PMBus,SMBus) I3C SPI D²B ParallelSCSI Profibus IEEE1394(FireWire) USB CameraLink ExternalPCIe Thunderbolt Audio ADATLightpipe AES3 IntelHDAudio I²S MADI McASP S/PDIF TOSLINK Portable PCCard ExpressCard Embedded Multidropbus CoreConnect AMBA(AXI) Wishbone SLIMbus Interfacesarelistedbytheirspeedinthe(roughly)ascendingorder,sotheinterfaceattheendofeachsectionshouldbethefastest.Category Retrievedfrom"https://en.wikipedia.org/w/index.php?title=Compute_Express_Link&oldid=1058162570" Categories:Computer-relatedintroductionsin2019PeripheralComponentInterconnectSerialbusesMotherboardexpansionslotHiddencategories:ArticleswithshortdescriptionShortdescriptionisdifferentfromWikidataOfficialwebsitedifferentinWikidataandWikipedia Navigationmenu Personaltools NotloggedinTalkContributionsCreateaccountLogin Namespaces ArticleTalk Variants expanded collapsed Views ReadEditViewhistory More expanded collapsed Search Navigation MainpageContentsCurrenteventsRandomarticleAboutWikipediaContactusDonate Contribute HelpLearntoeditCommunityportalRecentchangesUploadfile Tools WhatlinkshereRelatedchangesUploadfileSpecialpagesPermanentlinkPageinformationCitethispageWikidataitem Print/export DownloadasPDFPrintableversion Languages Suomi Editlinks