What is a RAM Bank? How is it defined? - Super User

So a RAM Bank (or RAM Module) is a circuit board, containing gold connection points and RAM chips and is used in computers to temporarily ... SuperUserisaquestionandanswersiteforcomputerenthusiastsandpowerusers.Itonlytakesaminutetosignup. Signuptojointhiscommunity Anybodycanaskaquestion Anybodycananswer Thebestanswersarevotedupandrisetothetop Home Public Questions Tags Users Unanswered FindaJob Jobs Companies Teams StackOverflowforTeams –Collaborateandshareknowledgewithaprivategroup. CreateafreeTeam WhatisTeams? Teams CreatefreeTeam Teams Q&Aforwork Connectandshareknowledgewithinasinglelocationthatisstructuredandeasytosearch. Learnmore WhatisaRAMBank?Howisitdefined? AskQuestion Asked 5years,1monthago Active 8monthsago Viewed 10ktimes 0 1 I'vebeenlookingaround,andIcan'tseemtogetasolidansweronwhataMemoryBankisinRAM.Somesaythatit'ssomethinglikeachannel,otherslikeaDIMMslot,otherssayit'sjustanarbitraryandnonstandarddivisionofmemory,oritmaybeasubdivisionofachip,withmanymemorybanksperchip. Iwouldtendtoleantowardsthelastargumentbeingthecorrectone,basedonmyresearch,buthowisthesizeoftheBankdetermined?Further,howdotheydecidehowmanybanksfitinachip,andisittruethatonlyonebankcanbeaccessedperread/write? Ifthisisthecasethenmyunderstandingofhowthememorybusisdividedamongthechipsmustbeincorrect(64bitdatabus/8chips=8bitbustoeachchip,thatonlyuses1/8thoftheentirememorybus,sowhycan'totherchipsbeaccessedatthesametimetofilltherestofthebus?) memorycomputer-architecture Share Improvethisquestion Follow editedOct9'16at1:36 SathyajithBhat♦ 60.4k3636goldbadges176176silverbadges263263bronzebadges askedOct8'16at15:01 ChrømeChrøme 1111silverbadge11bronzebadge 1 It'snotastandardtermanddependsonthesystemyou'retalkingabout. – Joseph Mar6at9:34 Addacomment  |  2Answers 2 Active Oldest Votes 1 ThetermRAMBankisnotreallyastandardterm,butpeopleoftenuseittorefertomemorymodules.Youknow,thosestripsyoucanbuythatcomeinvarioussizesofmemory,arerectangularshapedandhasmanygoldenconnectionpointsandasmallholecutinbetweentomakesureitonlyfitsthecorrectmemoryslot. RAMstandsfor:RandomAccessMemory,whichisreferredtothecollectionofthismodule.RAMiswhatthismodulecontains.ThetermRandomAccessisusedbecausenotonlycanthememorybeenread,itcanalsobeenwrittentoanderased.ThereisalsothetermROM:Read-OnlyMemory,whicharememorychipswho'svaluescanonlyberead,notwrittento. TheterminologyforBank,Module,Bararethingspeopleuse.Moduleistheofficialname,butbothbankandbararecommonlyusedduetonotknowingtheproperterminology. SoaRAMBank(orRAMModule)isacircuitboard,containinggoldconnectionpointsandRAMchipsandisusedincomputerstotemporarilyrememberanydataonthecomputer,forexamplewhatthewindowlookslike,whichgraphicsitsdisplaying,itsallstoredinRAM,inoneoftheRAMbanks/RAMModules. Share Improvethisanswer Follow answeredOct8'16at15:09 LPChipLPChip 51.7k88goldbadges8181silverbadges117117bronzebadges 3 Soisthereanysubdivisionofachipthatyouknowofbeforeyougetdowntotheindividualcelllevel?I'mthinkingalongthelinesofthatyoucan'tmakethewordlinestoolong(forsignalpropagation)orthebitlinestoolong(forcapacitance),sodotheyjustlimitthesizeofthechiptoaddressthat? – Chrøme Oct8'16at15:32 Yes,butitsnotnecessarytoknowforyourquestionanditwillmakeitfartobroad.Basicallythechipcanhavedifferentaccesstypes,suchasRAMandROMorflash,EEPROM,etc,andwhatitisusedfor(aka,itsfunction)canbedifferentforeverychip. – LPChip Oct8'16at15:41 Wellsure,itisn'tnecessary,butI'dstilllovetoknow.IthinkIunderstandtheconceptofthedifferentaccesstypes,butwhatI'mnotclearonishowthatrelatestothe(possible)subdivisionsofachipandcontrollingthesizesofthebitandwordlines? – Chrøme Oct8'16at15:51 Addacomment  |  1 Acoherent'system'addressonmodernIntelCPUsissenttothecorrecthomeagent(memorycontroller)bytheCBoLLCslicecontrollertowhichthataddressisoriginallyinterleavedto.ThecorrecthomeagentisselectedbasedonCBoSADinterleaverules,andthebitsoftheaddressthatareusedtointerleavetheaddresstothehomeagentareremovedfromtheaddresswhensentandwouldhavebeenwithinthecolumnpartoftheaddress;thehomeagentthenusestheaddresstoselectthecorrectlogicalchannelusingTADinterleavingrules(TAD_DRAM_RULE_0–7for8separaterangesthatcanbeconfigured,whichselectsalogicalchannelinthecorrespondingTAD_INTERLEAVE_LIST_0);thelogicalchannelisthenconvertedtothecorrectphysicalchannelusingtheCHMlogicaltophysicalone-to-onemappingregister(MC_CHANNEL_MAPPER),andfinallytheaddressisconvertedtoachanneladdressonthatphysicalchannelusingthecorrespondingSAGrule(MC_SAG_CH0_0),whichsimplyremovesthebitsusedtointerleavetothechannelintheTADDRAMrule,whichwouldhavebeenpartofthecolumnpartoftheaddress.Theresultingaddressiscalledthechanneladdressandisoftheformat: rank[z:0],bankgroup[1:0]([0]onx16),bank[1:0],row[y:0],column[9:0],offset[x:0](xis3onx4,2onx8and3onx16) Therank,bankgroupandbankaddresspinsselectabankonthecorrectrankonthecorrectmodule.TheSkylakeCPUontheAsusGL502VMgaminglaptophas4chipselectselectpinsperchannelandoneSO-UDIMMslotperchannel,andselectranksontheSO-UDIMM,meaningthereareamaximumof4ranksusingthechipselectpinsonDDR4.Eachchannelalsohas2bankgroupselectpinsand2bankaddressselectpins,andtheseselectabankontherank.EachsideoftheDIMMhasitsownclock. OnaDDR4DIMM,therankconstitutestheDRAMchips/diesononesideoftheDIMM,orifitusing3DS2H,4H,and8Hstacksthrough-siliconvias(TSVs)theneachrankisalayer.A2HDIMMhas2layersoneitherside(itsDRAMchipsareDDPs),meaningitcanbe4rankanduses4chipselectsCS0toCS3,thisinternallymanifestsasCS0AorCSOB,CS1A,CS1Bandsoonbasedonwhathalfoftherankthebanklieson.A2HcanalsousechipselectsCS0andCS1toselectaphysicalrank(packagerank)andthenuseC0toselectthelogicalrank(layer)withinthephysicalrank,ratherthanhavingachipselectforeachlogicalrank.A4Hcoulduse8logicalranksusingtheCS0+C[2:0]scheme(CS0selectsthemoduleandC0isonCS2;C1isonCS3;andC2isonNCandareusedtosendaChipID).Theoretically,DDR4allowsupto32rankswith4chipselectsselectingpackageranksand8logicalrankseach.A4HDIMMcanbe8ranksifeachsideoftheDIMMisarank,andinthiscaseneedstousethelogicalChipIDinsomemanner.CS2andCS3arenotusedonUDIMMs,whicharetypicallydualrank--I'mnotsurewhetherUDIMMseverusealogicalChipIDlikeRDIMMsorLRDIMMsdo. Abankgroupselectsasetofbanksandthebankaddressselectsthebankwithinthebankgroup.Thebankandbankgroupintheaboveformatishigh-orderinterleavedontherowbutitcanbeconfiguredtobelow-orderinterleavedonsomemodules. EachbankislogicallysplitacrosstheDRAMchipsandhasaglobalrow/columndecoderandrowbuffer(senseamplifiers)perDRAMchip.Thesectionofthebanklocaltoachipisa2Darrayof2Dsubarraysconnectedbyglobalbitlinesandglobalwordlines.Eachsubarrayhasalocalrow/columndecoderandstoragecellsconnectedwithwordlines,bitlines,senseamplifiers,writedrivers,prechargedrivers.AbankisspreadacrosstheDRAMchipswhereeachchipprovidesaword(x4,x8,x16)fromthecolumn(wherethecolumnconstitutes64bits/storagecells(128storagecellswithcomplementary/dummystoragecellsfordifferentialsenseamplifier)),andtheoffsetselectsthecorrectchipintherank.Locallytothechip,thecolumnconstitutesonlythewordthatbelongstothechipandthereforethereareeither4,8or16wordlinespercolumnlocally,but64perrank. Youhavetoprechargethebitlinesinabank(whichwilldosoonallchipsthatcontainthelogicalbankinparallel)beforeaccessingacolumninadifferentrowtotheoneopeninthesamebank,whichdrivesthebitlinesforeachcolumnbacktoVDD/2sothatanotherrowisreadytobeopened.Beforeaprecharge,RASisdeassertedtoclosetheopenrowwordline.Theredoesn'tneedtobea'writeback'oftherowbuffer(page),becauseuponwrites,thedataiswrittendirectlytothecell,andthenthesenseamplifierisreenabledtoreflectthechangeontheoutput. Share Improvethisanswer Follow editedMar7at18:47 answeredMar6at1:27 LewisKelseyLewisKelsey 37611silverbadge1212bronzebadges Addacomment  |  YourAnswer ThanksforcontributingananswertoSuperUser!Pleasebesuretoanswerthequestion.Providedetailsandshareyourresearch!Butavoid…Askingforhelp,clarification,orrespondingtootheranswers.Makingstatementsbasedonopinion;backthemupwithreferencesorpersonalexperience.Tolearnmore,seeourtipsonwritinggreatanswers. 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